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Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
f POLE 2 =
1
2 π ( C BE + C Q 4 IN ) × R IN || R 12
tance, reduces the frequency of the second pole (f POLE2 )
that could destabilize the linear regulator (see the Stability
Requirements section). Therefore, the stability require-
ments determine the maximum base-to-emitter capaci-
If the second pole occurs well after unity-gain
crossover, the linear regulator remains stable. If not,
then increase the output capacitance C OUT3 (C8 in the
Typical Applications Circuits ) so:
f POLE 2 > 2 × f C _ OUT 3 _
If high-ESR capacitors are used for the output capaci-
tor (C OUT3 ), then cancel the ESR zero with a pole at
FB3_. This is accomplished by adding a capacitor
(C FB3_ ) from FB3_ to GND so:
tance (C BE ) that can be added.
Transformer Selection
In systems where the step-down controller ’s output
(OUT1) is not the highest voltage, a transformer can be
used to provide additional post-regulated, high-voltage
outputs. The transformer generates unregulated high-
voltage supplies that power the positive and negative
linear regulators. These unregulated supply voltages
must be high enough to keep the pass transistors from
saturating. For positive output voltages, connect the
transformer as shown in the Typical Applications
C FB 3 _ =
1
2 π × R 3 || R 4 × f ESR
Circuits where the minimum turns ratio (n 2 /n 1 ) is deter-
mined by:
OUT3_ Output Capacitors
n 2
n 1
≥
V OUT 3 _ + V Q 4 ( SAT ) + V D 2
V OUT 1
Connect at least a 1μF capacitor between the linear regu-
lator’s output and ground, as close to the MAX8513/
MAX8514 and the external pass transistors as possible.
Depending on the selected pass transistor, larger capaci-
tor values may be required for stability (see the Stability
Requirements section). Once the minimum capacitor
value for stability is determined, verify that the linear regu-
lator’s output does not contain excessive noise. Although
adequate for stability, small capacitor values can provide
too much bandwidth, making the linear regulator sensitive
to noise. Larger capacitor values reduce the bandwidth,
thereby reducing the regulator’s noise sensitivity. For the
negative linear regulator, if noise on the ground reference
causes the design to be marginally stable, bypass the
negative output back to its reference voltage (V REF3N ,
Figure 6). This technique reduces the differential noise on
the output. Ensure the voltage rating of the capacitor
exceeds the output voltage.
Base-Drive Noise Reduction
The high-impedance base driver is susceptible to system
noise, especially when the linear regulator is lightly
loaded. Capacitively coupled switching noise or induc-
where V Q4(SAT) is OUT3P’s pass transistor’s saturation
voltage under full load. Since power transfer occurs
when the low-side MOSFET is on (DL = high), the trans-
former cannot support heavy loads with high duty
cycles on V OUT1 .
Minimum Load Requirements
(Linear Regulators)
Under no-load conditions, leakage currents from the
pass transistors supply the output capacitor, even
when the transistor is off. Generally, this is not a prob-
lem since the feedback resistors’ current drains the
excess charge. However, charge can build up on the
output capacitor over temperature, making V OUT2/3 rise
above its set point. Care must be taken to ensure the
feedback resistors’ current exceeds the pass transis-
tor’s leakage current over the entire temperature range.
Thermal Consideration
The power dissipated by the series pass transistor is
calculated by:
tively coupled EMI on the base drive causes fluctuations
in the base current, which appear as noise on the linear
regulator’s output. To avoid this, keep the base-drive
P D =
( | V IN - V OUT 2 / 3 | ) × I OUT 2 / 3
traces away from the step-down converter and as short
as possible to minimize noise coupling. Resistors in
series with the gate drivers (DH and DL) reduce the LX
switching noise generated by the step-down converter.
Additionally, a bypass capacitor (C BE ) can be placed
across the base-to-emitter resistor (Figure 7). This bypass
capacitor, in addition to the transistor’s input capaci-
where V IN is the input to the transistor of the LDO and
the absolute value of the difference between V IN and
V OUT2/3 is taken. V IN is derived from the transformer
winding ratio. The transistor must be adequately heat
sunk to prevent a thermal runaway condition. Refer to
the transistor data sheet for thermal calculation.
30
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